
Part 2: Flip-Flops, Timing Parameters and Synchronization
Many digital systems must process signals from outside from sensors and level translators. The signals are mostly pulse trains or bursts of pulses. Some pulses may be too narrow, some may be too wide, and other pulse trains may be affected by glitches. Designers need to learn about capturing pulses, detecting edges, filtering out or detecting glitches, and synchronizing the pulses with internal clocks. In the first part of this three-part article, we introduced the latches and flip-flops as the most basic components to address these fundamental design problems. This month, we examine how to enable and disable flipflops, timing parameters and synchronization. These are minor but intricate problems most textbooks do not cover. Solving such problems requires some familiarity with the appropriate components and some inclination to deal with the utmost details.
ENABLING AND DISABLING FLIP-FLOPS
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Esta historia es de la edición January 2025 de Circuit Cellar.
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