Mitigate Timing and Interference Issues on Multicore Processors

Missing multicore timing deadlines in a driver safety or aviation system is potentially catastropic. Adhering to guidance documents, and employing the appropriate testing and analysis methods ensures the efficient and deterministic execution of critical workloads.

- Steve DiCamillo

Embedded software developers face unique challenges when dealing with timing and interference issues on heterogeneous multicore processor (MCP) based systems. Such systems offer higher CPU workload capacity and performance than single core processor (SCP) setups, but their complexity can make strict timing requirements extremely difficult to meet.

In hard real-time systems, deterministic execution is crucial for meeting operational and safety goals. Although MCP-based systems generally exhibit lower average execution times for a given set of tasks than do SCP systems, the distribution of these times is more variable.

This makes it difficult for developers to ensure precise timing for tasks, creating significant problems when they are building applications where meeting the worst execution times for individual tasks is more critical than meeting goals for average times.

To address such challenges, embedded software developers can turn to guidance documents like CAST-32A, AMC 20-193, and AC 20-193. In CAST-32A, the Certification Authorities Software Team (CAST) outlines important considerations for MCP timing and sets Software Development Life Cycle (SDLC) objectives for a better understanding of the behavior of a multicore system. While not prescriptive requirements, these objectives guide and support developers toward adhering to widely accepted standards like DO-178C.

In Europe, the AMC 20-193 document has superseded and replaced CAST-32A, and in the U.S., the AC 20-193 document has done the same. These successor documents, collectively referred to as A(M)C 20-193, largely duplicate the principles outlined in CAST-32A.

To apply the guidance from A(M)C 20-193, developers can employ various techniques for measuring timing and interference on MCPbased systems.

WORST-CASE EXECUTION TIMING